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2.5V 18M-BIT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS 524,288 x 36
IDT72T36135M
* * * * * * * * * * * * *
FEATURES:
* * * * * * * * * * *
Industry's largest FIFO memory organization: IDT72T36135 524,288 x 36 - 18M-bits Up to 200 MHz Operation of Clocks Functionally and pin compatible to 9Mbit IDT72T36125 TeraSync devices User selectable HSTL/LVTTL Input and/or Output User selectable Asynchronous read and/or write port timing Mark & Retransmit, resets read pointer to user marked position Write Chip Select (WCS) input disables Write Port Read Chip Select (RCS) synchronous to RCLK Programmable Almost-Empty and Almost-Full flags, each flag can default to one of eight preselected offsets Program programmable flags by either serial or parallel means Selectable synchronous/asynchronous timing modes for AlmostEmpty and Almost-Full flags
Separate SCLK input for Serial programming of flag offsets Auto power down minimizes standby power consumption Master Reset clears entire FIFO Partial Reset clears data, but retains programmable settings Empty and Full flags signal FIFO status Select IDT Standard timing (using EF[1:2] and FF[1:2] flags) or First Word Fall Through timing (using OR[1:2] and IR[1:2] flags) Output enable puts data outputs into high impedance state JTAG port, provided for Boundary Scan function Available in 240-pin (19mm x 19mm)Plastic Ball Grid Array (PBGA) 50% more space saving than the leading 9M-bit FIFOs Independent Read and Write Clocks (permit reading and writing simultaneously) High-performance submicron CMOS technology Industrial temperature range (-40C to +85C) is available Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
D0 -Dn (x36)
WEN WCLK/WR WCS LD SEN SCLK
INPUT REGISTER
OFFSET REGISTER
FF/IR[1:2] PAF[1:2] EF/OR[1:2] PAE[1:2] FWFT/SI PFM FSEL0 FSEL1
ASYW
WRITE CONTROL LOGIC
FLAG LOGIC RAM ARRAY 524,288 x 36 READ POINTER
WRITE POINTER
MRS PRS TCK TRST TMS TDO TDI Vref WHSTL RHSTL SHSTL
RESET LOGIC
JTAG CONTROL (BOUNDARY SCAN)
OUTPUT REGISTER
READ CONTROL LOGIC
RT MARK ASYR
HSTL I/0 CONTROL
RCLK/RD REN RCS
OE
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Q0 -Qn (x36)
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 1
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2006
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
A1 BALL PAD CORNER
A
VCC VCC VCC VCC VCC VCC WCLK PRS GND FF1 FF2 RCLK OE VDDQ VDDQ VDDQ VDDQ VDDQ
B
VCC VCC VCC VCC VCC VCC WEN MRS GND PAF1 EF1 REN RCS VDDQ VDDQ VDDQ VDDQ VDDQ
C
VCC VCC VCC VCC VCC VCC WCS LD GND PAF2 PAE1 MARK RT VDDQ VDDQ VDDQ VDDQ VDDQ
D
VCC VCC VCC FWFT/SI DNC FSEL0 SHSTL FSEL1 GND GND PAE2 EF2 RHSTL ASYR PFM VDDQ VDDQ VDDQ
E
VCC VCC VCC GND GND VDDQ VDDQ VDDQ
F
VCC VCC VCC GND GND VDDQ VDDQ VDDQ
G
VCC SEN SCLK WHSTL GND VDDQ VDDQ VDDQ
H
VCC VCC VCC ASYW GND GND GND GND GND VDDQ VDDQ VDDQ
J
VCC VCC VCC VREF GND GND GND GND GND VDDQ VDDQ VDDQ
K
VCC VCC VCC DNC GND GND GND GND GND VDDQ VDDQ VDDQ
L
D33 D34 D35 GND GND GND GND GND GND VDDQ Q35 Q34
M
D30 D31 D32 GND GND Q33 Q32 Q31
N
D27 D28 D29 GND GND Q30 Q29 Q28
P
D24 D25 D26 GND GND Q27 Q26 Q25
R
D21 D22 D23 GND GND GND GND GND GND GND GND GND GND GND GND Q24 Q23 Q22
T
D19 D20 D13 D10 D5 D4 D1 TMS TDO GND Q0 Q2 Q3 Q8 Q11 Q14 Q21 Q20
U
D18 D17 D14 D11 D7 D8 D2 TRST TDI GND Q1 Q6 Q5 Q9 Q12 Q15 Q18 Q19
V
VCC D16 D15 D12 D9 D6 D3 D0 TCK GND DNC Q4 Q7 Q10 Q13 Q16 Q17 VDDQ
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NOTE: 1. DNC - Do Not Connect.
PBGA: 1mm pitch, 19mm x 19mm (BB240-1, order code: BB) TOP VIEW
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT72T36135M is an exceptionally deep, extrememly high speed, CMOS First-In-First-Out (FIFO) memoriy with clocked read and write controls and a wide extended x36 bus to allow ample data flow. These FIFOs offer several key user benefits: * High density offering of 18 Mbit * 200MHz R/W Clocks supporting 7.2Gbps of data throughput * User selectable MARK location for retransmit * User selectable I/O structure for HSTL or LVTTL * Asynchronous/Synchronous translation on the read or write ports * The first word data latency period, from the time the first word is written to an empty FIFO to the time it can be read, is fixed and short. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data at very high performance. The input port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the input port is controlled by a Write Clock (WCLK) input and a Write Enable (WEN) input. Data present on the Dn data inputs is written into the FIFO on every rising edge of WCLK when WEN is asserted. During Asynchronous operation only the WR input is used to write data into the FIFO. Data is written on a rising edge of WR, the WEN input should be tied to its active state, (LOW). The input port can be selected for either 2.5V LVTTL or HSTL operation, this operation is selected by the state of the WHSTL input during a master reset. A Write Chip Select input (WCS) is provided for use when the write port is in both LVTTL and HSTL modes. During operation the WCS input can be used to disable write port inputs (data only). The output port can be selected as either a Synchronous (clocked) interface, or Asynchronous interface. During Synchronous operation the output port is controlled by a Read Clock (RCLK) input and Read Enable (REN) input. Data is read from the FIFO on every rising edge of RCLK when REN is asserted. During Asynchronous operation only the RD input is used to read data from the FIFO. Data is read on a rising edge of RD, the REN input should be tied to its active state, LOW. When Asynchronous operation is selected on the output port the FIFO must be configured for Standard IDT mode, also the RCS should be tied LOW and the OE input used to provide three-state control of the outputs, Qn. The output port can be selected for either 2.5V LVTTL or HSTL operation, this operation is selected by the state of the RHSTL input during a master reset. An Output Enable (OE) input is provided for three-state control of the outputs. A Read Chip Select (RCS) input is also provided, the RCS input is synchronized to the read clock, and also provides three-state control of the Qn data outputs. When RCS is disabled, the data outputs will be high impedance. During Asynchronous operation of the output port, RCS should be enabled, held LOW. The frequencies of both the RCLK and the WCLK signals may vary from 0 to fMAX with complete independence. There are no restrictions on the frequency of the one clock input with respect to the other. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. In IDT Standard mode, the first word written to an empty FIFO will not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN and enabling a rising RCLK edge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A REN does not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. 3
For applications requiring more data storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. The 18M-bit TeraSync FIFO has 8 flag pins, EF/OR[1:2] (Empty Flag or Output Ready), FF/IR[1:2] (Full Flag or Input Ready), PAE[1:2] (Programmable Almost-Empty flag) and PAF[1:2] (Programmable Almost-Full flag). The EF[1:2] and FF[1:2] functions are selected in IDT Standard mode. The IR[1:2] and OR[1:2] functions are selected in FWFT mode. PAE[1:2] and PAF[1:2] are always available for use, irrespective of timing mode. Each flag has a double because the 18M FIFO was designed as a Multi-chip Module, so each set of flags supports its respective internal 9M FIFO. Some extra external gating logic will have to be used to accurately read each flag output. This will be covered in the flagging section of the datasheet. PAE[1:2] and PAF[1:2] can be programmed independently to switch at any point in memory. Programmable offsets determine the flag switching threshold and can be loaded by two methods: parallel or serial. Eight default offset settings are also provided, so that PAE[1:2] can be set to switch at a predefined number of locations from the empty boundary and the PAF[1:2] threshold can also be set at similar predefined values from the full boundary. The default offset values are set during Master Reset by the state of the FSEL0, FSEL1, and LD pins. For serial programming, SEN together with LD on each rising edge of SCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WEN together with LD on each rising edge of WCLK, are used to load the offset registers via Dn. REN together with LD on each rising edge of RCLK can be used to read the offsets in parallel from Qn regardless of whether serial or parallel offset loading has been selected. During Master Reset (MRS) the following events occur: the read and write pointers are set to the first location of the FIFO. The FWFT pin selects IDT Standard mode or FWFT mode. The Partial Reset (PRS) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable flag programming method, and default or programmed offset settings existing before Partial Reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable. It is also possible to select the timing mode of the PAE[1:2] (Programmable Almost-Empty flag) and PAF[1:2] (Programmable Almost-Full flag) outputs. The timing modes can be set to be either asynchronous or synchronous for the PAE[1:2] and PAF[1:2] flags. If asynchronous PAE/PAF[1:2] configuration is selected, the PAE[1:2] is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE[1:2] is reset to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF[1:2] is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF[1:2] is reset to HIGH on the LOW-to-HIGH transition of RCLK. If synchronous PAE/PAF[1:2] configuration is selected , the PAE[1:2] is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF[1:2] is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during MasterReset by the state of the Programmable Flag Mode (PFM) pin. This device includes a Retransmit from Mark feature that utilizes two control inputs, MARK and , RT (Retransmit). If the MARK input is enabled with respect to the RCLK, the memory location being read at that point will be marked. Any subsequent retransmit operation, RT goes LOW, will reset the read pointer to this `marked' location. If, at any time, the FIFO is not actively performing an operation, the chip will automatically power down. Once in the power down state, the standby supply current consumption is minimized. Initiating any operation (by activating control
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
inputs) will immediately take the device out of the power down state. Both an Asynchronous Output Enable pin (OE) and Synchronous Read Chip Select pin (RCS) are provided on the FIFO. The Synchronous Read Chip Select is synchronized to the RCLK. Both the output enable and read chip select control the output buffer of the FIFO, causing the buffer to be either HIGH impedance or LOW impedance. A JTAG test port is provided, here the FIFO has fully functional Boundary Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and Boundary Scan Architecture. Special consideration should be taken into
account for JTAG testing since the device is a MCM. Please see JTAG section for further details. The TeraSync FIFO has the capability of operating its ports (write and/or read) in either LVTTL or HSTL mode, each ports selection independent of the other. The write port selection is made via WHSTL and the read port selection via RHSTL. An additional input HSTL is also provided, this allows the user to select HSTL operation for other pins on the device (not associated with the write or read ports). The IDT72T36135M is fabricated using IDT's high speed submicron CMOS technology.
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PARTIAL RESET (PRS)
MASTER RESET (MRS)
WRITE CLOCK (WCLK/WR) WRITE ENABLE (WEN) WRITE CHIP SELECT (WCS) LOAD (LD) (x36) DATA IN (D0 - Dn) SERIAL CLOCK (SCLK) SERIAL ENABLE(SEN) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) FULL FLAG/INPUT READY (FF/IR[1:2]) PROGRAMMABLE ALMOST-FULL (PAF[1:2]) IDT 72T36135M
READ CLOCK (RCLK/RD) READ ENABLE (REN) OUTPUT ENABLE (OE) READ CHIP SELECT (RCS) (x36) DATA OUT (Q0 - Qn) RCLK REN MARK RETRANSMIT (RT) EMPTY FLAG/OUTPUT READY (EF/OR[1:2]) PROGRAMMABLE ALMOST-EMPTY (PAE[1:2])
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Figure 1. Single Device Configuration Signal Flow Diagram
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION
Symbol Name I/O TYPE LVTTL INPUT LVTTL INPUT Description A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode. A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW will select Asynchronous operation. ASYR(1) Asynchronous Read Port ASYW(1) Asynchronous Write Port D0-D35 Data Inputs EF/OR Empty Flag/ [1:2] Output Ready FF/IR [1:2] Full Flag/ Input Ready
HSTL-LVTTL Data inputs for a 36-bit bus. INPUT HSTL-LVTTL In the IDT Standard mode, the EF[1:2] function is selected. EF[1:2] indicates whether or not the FIFO memory OUTPUT is empty. In FWFT mode, the OR[1:2] function is selected. OR[1:2] indicates whether or not there is valid data available at the outputs. Please see Flagging section for external gating instructions of these flags. HSTL-LVTTL In the IDT Standard mode, the FF[1:2] function is selected. FF[1:2] indicates whether or not the FIFO memory OUTPUT is full. In the FWFT mode, the IR[1:2] function is selected. IR[1:2] indicates whether or not there is space available for writing to the FIFO memory. Please see Flagging section for external gating instructions of these flags. LVTTL INPUT LVTTL INPUT During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the programmable flags PAE[1:2] and PAF[1:2]. There are up to eight possible settings available. During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the programmable flags PAE[1:2] and PAF[1:2]. There are up to eight possible settings available.
FSEL0(1) Flag Select Bit 0 FSEL1(1) Flag Select Bit 1 FWFT/ SI LD First Word Fall Through/Serial In Load
HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin INPUT functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been selected then the FIFO must be set-up in IDT Standard mode. HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1, INPUT determines one of eight default offset values for the PAE[1:2] and PAF[1:2] flags, along with the method by which these offset registers can be programmed, parallel or serial (see Table 1). After Master Reset, this pin enables writing to and reading from the offset registers.
MARK MRS
Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit INPUT operation will reset the read pointer to this position. Master Reset HSTL-LVTTL MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master INPUT Reset, the FIFO is configured for either FWFT or IDT Standard mode,Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings, serial or parallel programming of the offset settings, zero latency timing mode, and synchronous versus asynchronous programmable flag timing modes. HSTL-LVTTL OE provides Asynchronous three-state control of the data outputs, Qn. During a Master or Partial Reset the INPUT OE input is the only input that provide High-Impedance control of the data outputs.
OE PAE [1:2] PAF [1:2] PFM(1) PRS
Output Enable
Programmable HSTL-LVTTL PAE[1:2] goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Almost-Empty Flag OUTPUT Empty Offset register. PAE[1:2] goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n. Please see Flagging section for external gating instructions of these flags. Programmable Almost-Full Flag Programmable Flag Mode Partial Reset HSTL-LVTTL PAF[1:2] goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored OUTPUT in the Full Offset register. PAF[1:2] goes LOW if the number of free locations in the FIFO memory is less than or equal to m. Please see Flagging section for external gating instructions of these flags. LVTTL INPUT During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable flag timing mode.
HSTL-LVTTL PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset, INPUT the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained. HSTL-LVTTL Data outputs for an 36-bit bus. OUTPUT HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by REN, the rising edge of RCLK INPUT reads data from the FIFO memory and offsets from the programmable registers. If LD is LOW, the values loaded into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read 6
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Q0-Q35 Data Outputs RCLK/ RD Read Clock/ Read Stobe
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN DESCRIPTION (CONTINUED)
Symbol Name RCLK/ Read Clock/ RD Read Strobe RCS Read Chip Select I/O TYPE Description HSTL-LVTTL port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. INPUT REN should be tied LOW. HSTL-LVTTL RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During INPUT a Master Reset or Partial Reset the RCS input is don't care, if OE is LOW the data outputs will be Low-Impedance regardless of RCS. HSTL-LVTTL If Synchronous operation of the read port has been selected, REN enablesRCLK for reading data from the INPUT FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the REN input should be tied LOW. LVTTL INPUT This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL inputs are required, this input must be tied HIGH. Otherwise it should be tied LOW.
REN
Read Enable
RHSTL(1) Read Port HSTL Select RT Retransmit
HSTL-LVTTL RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF[1:2] flag to LOW INPUT (OR[1:2] to HIGH in FWFT mode) and doesn't disturb the write pointer, programming method, existing timing mode or programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump to the `mark' location. HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that INPUT SEN is enabled. HSTL-LVTTL SEN enables serial loading of programmable flag offsets. INPUT LVTTL INPUT All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
SCLK SEN SHSTL TCK(2) TRST(2) TMS TDI TDO WEN
Serial Clock Serial Enable System HSTL Select JTAG Clock JTAG Reset JTAG Mode Select Test Data Input Test Data Output Write Enable
HSTL-LVTTL Clock input for JTAG function. TMS and TDI are sampled on the rising edge of TCK. Data is output on INPUT TDO on the falling edge. HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. INPUT HSTL-LVTTL TMS is a serial input pin. Bits are serially loaded on the rising edge of TCK, which selects 1 of 5 modes of INPUT operation for the JTAG boundary scan. HSTL-LVTTL During JTAG boundary scan operation test data is serially loaded via TDI on the rising edge of TCK. INPUT This is also the data for the Instruction Register, ID Register and Bypass Register. HSTL-LVTTL During JTAG boundary scan operation test data is serially output via TDO on the falling edge of TCK. OUTPUT This output is in High-Z except when shifting, while in SHIFT-DR and SHIFT-IR controller states. HSTL-LVTTL When Synchronous operation of the write port has been selected, WEN enables WCLK for writing data into INPUT theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the WEN input should be tied LOW. HSTL-LVTTL This pin disables the write port data inputs when the device write port is configured for HSTL mode. This INPUT provides added power savings. HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by WEN, the rising edge of INPUT WCLK writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state). LVTTL INPUT Power GND I This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must be tied HIGH. Otherwise it should be tied LOW. These are Vcc supply inputs and must be connected to the 2.5V supply rail. These are Ground pins an dmust be connected to the GND rail. This is a Voltage Reference input and must be connected to a voltage level determined from the table, "Recommended DC Operating Conditions". This provides the reference voltage when using HSTL class inputs. If HSTL class inputs are not being used, this pin should be tied LOW. This pin should be tied to the desired voltage rail for providing power to the output drivers.
WCS WCLK/ WR
Write Chip Select Write Clock/ Write Strobe
WHSTL(1) Write Port HSTL Select Vcc GND Vref +2.5v Supply Ground Pin Reference Voltage O/P Rail Voltage
VDDQ
I
NOTES: 1. Inputs should not change state after Master Reset. 2. If the JTAG feature is not being used, TCK and TRST should be tied LOW.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
Symbol VTERM TSTG IOUT Rating Terminal Voltage with respect to GND Storage Temperature DC Output Current Commercial -0.5 to +3.6(2) -55 to +125 -50 to +50 Unit V
CAPACITANCE (TA = +25C, f = 1.0MHz)
Symbol CIN
(2,3)
Parameter(1) Input Capacitance Output Capacitance
Conditions VIN = 0V VOUT = 0V
Max. 15
(3)
Unit pF pF
C
mA
COUT(1,2)
10.5
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Compliant with JEDEC JESD8-5. VCC terminal only.
NOTES: 1. With output deselected, (OE VIH). 2. Characterized values, not currently tested. 3. CIN for Vref is 40pF.
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH Parameter Supply Voltage Supply Voltage Input High Voltage LVTTL eHSTL HSTL LVTTL eHSTL HSTL eHSTL HSTL Min. 2.375 0 1.7 VREF+0.2 VREF+0.2 -0.3 -0.3 -0.3 0.8 0.68 0 -40 Typ. 2.5 0 -- -- -- -- -- -- 0.9 0.75 -- -- Max. 2.625 0 3.45 VDDQ+0.3 VDDQ+0.3 0.7 VREF-0.2 VREF-0.2 1.0 0.9 70 85 Unit V V V V V V V V V V
VIL
Input Low Voltage
VREF(1) TA TA
Voltage Reference Input
Operating Temperature Commercial Operating Temperature Industrial
C C
NOTE: 1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation. 2. Outputs are not 3.3V tolerant.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 2.5V 0.125V, TA = 0C to +70C;Industrial: VCC = 2.5V 0.125V, TA = -40C to +85C)
Symbol ILI ILO VOH(5) Input Leakage Current Output Leakage Current Output Logic "1" Voltage, IOH = -8 mA IOH = -8 mA IOH = -8 mA IOL = 8 mA IOL = 8 mA IOL = 8 mA I/O = LVTTL I/O = HSTL I/O = eHSTL I/O = LVTTL I/O = HSTL I/O = eHSTL @VDDQ = 2.5V 0.125V (LVTTL) @VDDQ = 1.8V 0.1V (eHSTL) @VDDQ = 1.5V 0.1V (HSTL) @VDDQ = 2.5V 0.125V (LVTTL) @VDDQ = 1.8V 0.1V (eHSTL) @VDDQ = 1.5V 0.1V (HSTL) Parameter Min. -10 -10 VDDQ -0.4 VDDQ -0.4 VDDQ -0.4 -- -- -- -- -- -- -- -- -- Max. 10 10 -- -- -- 0.4V 0.4V 0.4V 120 180 180 40 140 140 Unit A A V V V V V V mA mA mA mA mA mA
VOL
Output Logic "0" Voltage,
ICC1(1,2)
Active VCC Current (VCC = 2.5V)
ICC2(1)
Standby VCC Current (VCC = 2.5V)
NOTES: 1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH. 2. For the IDT72T36105/72T36115/72T36135M, typical ICC1 calculation (with data outputs in Low-Impedance): -3. For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz) with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000 fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25C, N = Number of outputs switching. 4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ). 5. Outputs are not 3.3V tolerant.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS(1) -- SYNCHRONOUS TIMING
(Commercial: VCC = 2.5V 5%, TA = 0C to +70C;Industrial: VCC = 2.5V 5%, TA = -40C to +85C)
Commercial IDT72T36135ML5 Symbol fC tA tCLK tCLKH tCLKL tDS tDH tENS tENH tLDS tLDH tWCSS tWCSH fS tSCLK tSCKH tSCKL tSDS tSDH tSENS tSENH tRS tRSS tHRSS tRSR tRSF tWFF tREF tPAFS tPAES tRCSLZ tRCSHZ tSKEW1 tSKEW2 Parameter Clock Cycle Frequency (Synchronous) Data Access Time Clock Cycle Time Clock High Time Clock Low Time Data Setup Time Data Hold Time Enable Setup Time Enable Hold Time Load Setup Time Load Hold Time WCS setup time WCS hold time Clock Cycle Frequency (SCLK) Serial Clock Cycle Serial Clock High Serial Clock Low Serial Data In Setup Serial Data In Hold Serial Enable Setup Serial Enable Hold Reset Pulse Width(3) Reset Setup Time HSTL Reset Setup Time Reset Recovery Time Reset to Flag and Output Time Write Clock to FF[1:2] or IR[1:2] Read Clock to EF[1:2] or OR[1:2] Write Clock to Synchronous PAF[1:2] Read Clock to Synchronous PAE[1:2] RCLK to Active from High-Z(3) RCLK to High-Z(3) Skew time between RCLK and WCLK for EF[1:2] and FF[1:2] Skew time between RCLK and WCLK for PAE[1:2] and PAF[1:2] Min. -- 0.6 5 2.5 2.5 1.5 0.5 1.5 0.5 1.5 0.5 1.5 0.5 -- 100 45 45 15 5 5 5 10 15 4 10 -- -- -- -- -- -- -- -- -- Max. 200 3.6 -- -- -- -- -- -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- 15 3.6 3.6 3.6 3.6 3.6 3.6 4 5 Com'l & Ind'l IDT72T36135ML6 Min. -- 0.6 6 3.0 3.0 2.0 0.5 2.0 0.5 2.0 0.5 2.0 0.5 -- 100 45 45 15 5 5 5 10 15 4 10 -- -- -- -- -- -- -- -- -- Max. 166 3.8 -- -- -- -- -- -- -- -- -- -- -- 10 -- -- -- -- -- -- -- -- -- -- -- 15 3.7 3.7 3.7 3.7 3.7 3.7 5 6 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns MHz ns ns ns ns ns ns ns ns ns s ns ns ns ns ns ns ns ns ns ns
NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Pulse widths less than minimum values are not allowed. 3. Values guaranteed by design, not currently tested. 4. Industrial temperature range product for 6ns speed grade is available as a standard device. All other speed grades are available by special order.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS ASYNCHRONOUS TIMING
(Commercial: VCC = 2.5V 5%, TA = 0C to +70C;Industrial: VCC = 2.5V 5%, TA = -40C to +85C)
Commercial IDT72T36135ML5 Symbol fA tAA tCYC tCYH tCYL tRPE tFFA tEFA tPAFA tPAEA tOLZ tOE tOHZ tHF Parameter Cycle Frequency (Asynchronous) Data Access Time Cycle Time Cycle HIGH Time Cycle LOW Time Read Pulse after EF[1:2] HIGH Clock to Asynchronous FF[1:2] Clock to Asynchronous EF[1:2] Clock to Asynchronous Programmable Almost-Full Flag Clock to Asynchronous Programmable Almost-Empty Flag Output Enable to Output in Low Z(3) Output Enable to Output Valid Output Enable to Output in High Z(3) Clock to HF Min. -- 0.6 12 5 5 10 -- -- -- -- 0 -- -- -- Max. 83 10 -- -- -- -- 10 10 10 10 -- 3.6 3.6 10 Com'l & Ind'l IDT72T36135ML6 Min. -- 0.6 15 7 7 12 -- -- -- -- 0 -- -- -- Max. 66 12 -- -- -- -- 12 12 12 12 -- 3.8 3.8 12 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode. 2. Industrial temperature range product for 6ns speed grade is available as a standard device. All other speed grades are available by special order. 3. Values guaranteed by design, not currently tested.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
HSTL 1.5V AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels 0.25 to 1.25V 0.4ns 0.75 VDDQ/2
AC TEST LOADS
VDDQ/2 50 I/O Z0 = 50
10pF
6723 drw04
NOTE: 1. VDDQ = 1.5V.
Figure 2a. AC Test Load
EXTENDED HSTL 1.8V AC TEST CONDITIONS
tCD (Typical, ns)
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels 0.4 to 1.4V 0.4ns 0.9 VDDQ/2
6 5 4 3 2 1
NOTE: 1. VDDQ = 1.8V.
20 30 50
80 100 Capacitance (pF)
200
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2.5V LVTTL 2.5V AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels GND to 2.5V 1ns VCC/2 VDDQ/2
Figure 2b. Lumped Capacitive Load, Typical Derating
NOTE: 1. For LVTTL VCC = VDDQ.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OUTPUT ENABLE & DISABLE TIMING
Output Enable OE VIL Output Disable VIH
tOE & tOLZ Output VCC Normally 2 LOW
tOHZ VCC 2 VOL
100mV 100mV
Output Normally VCC 2 HIGH
NOTES: 1. REN is HIGH. 2. RCS is LOW.
100mV 100mV
VOH VCC 2
6723 drw05
READ CHIP SELECT ENABLE & DISABLE TIMING
RCS tENS RCLK tRCSLZ Output VCC Normally 2 LOW tRCSHZ VCC 2 VOL tENH VIH VIL
100mV 100mV
Output Normally VCC 2 HIGH
100mV 100mV
6723 drw06
VOH VCC 2
NOTES: 1. REN is HIGH. 2. OE is LOW.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH (FWFT) MODE The IDT72T36135M support two different timing modes of operation: IDT Standard mode or First Word Fall Through (FWFT) mode. The selection of which mode will operate is determined during Master Reset, by the state of the FWFT/SI input. If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF[1:2]) to indicate whether or not there are any words present in the FIFO. It also uses the Full Flag function (FF[1:2]) to indicate whether or not the FIFO has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK. If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR[1:2]) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR[1:2]) to indicate whether or not the FIFO has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK. Various signals, both input and output signals operate differently depending on which timing mode is in effect. IDT STANDARD MODE In this mode, the status flags, FF[1:2], PAF[1:2], PAE[1:2], and EF[1:2] operate in the manner outlined in Table 2. To write data into to the FIFO, Write Enable (WEN) must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of the Write Clock (WCLK). After the first write is performed, the Empty Flag (EF[1:2]) will go HIGH. Subsequent writes will continue to fill up the FIFO. The Programmable Almost-Empty flag (PAE[1:2]) will go HIGH after n + 1 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table 1. This parameter is also user programmable. See section on Programmable Flag Offset Loading. Continuing to write data into the FIFO will cause the Programmable AlmostFull flag (PAF[1:2]) to go LOW. Again, if no reads are performed, the PAF[1:2] will go LOW. The offset "m" is the full offset value. The default setting for these values are stated in the footnote of Table 1. This parameter is also user programmable. See section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF[1:2]) will go LOW, inhibiting further write operations. If no reads are performed after a reset, FF[1:2] will go LOW after D writes to the FIFO. If the FIFO is full, the first read operation will cause FF[1:2] to go HIGH. Subsequent read operations will cause PAF[1:2] to go HIGH at the conditions described in Table 2. If further read operations occur, without write operations, PAE[1:2] will go LOW when there are n words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, the EF[1:2] will go LOW inhibiting further read operations. REN is ignored when the FIFO is empty. When configured in IDT Standard mode, the EF[1:2] and FF[1:2] outputs are double register-buffered outputs. Relevant timing diagrams for IDT Standard mode can be found in Figure 10, 11, 12 and 17. FIRST WORD FALL THROUGH MODE (FWFT) In this mode, the status flags, IR[1:2], PAF[1:2], PAE[1:2], and OR[1:2] operate in the manner outlined in Table 3. To write data into to the FIFO, WEN must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO on subsequent transitions of WCLK. After the first write is performed, the Output Ready (OR[1:2]) flag will go LOW. Subsequent writes will continue to fill up the FIFO. PAE[1:2] will go HIGH after n + 2 words have been loaded into the FIFO, where n is the empty offset value. The default setting for these values are stated in the footnote of Table 1. This parameter is also user programmable. See section on Programmable Flag Offset Loading. When the FIFO is full, the Input Ready (IR[1:2]) flag will go HIGH, inhibiting further write operations. If no reads are performed after a reset, IR[1:2] will go HIGH after D writes to the FIFO. Note that the additional word in FWFT mode is due to the capacity of the memory plus output register. If the FIFO is full, the first read operation will cause the IR[1:2] flag to go LOW. Subsequent read operations will cause the PAF[1:2] to go HIGH at the conditions described in Table 3. If further read operations occur, without write operations, the PAE[1:2] will go LOW when there are n + 1 words in the FIFO, where n is the empty offset value. Continuing read operations will cause the FIFO to become empty. When the last word has been read from the FIFO, OR[1:2] will go HIGH inhibiting further read operations. REN is ignored when the FIFO is empty. When configured in FWFT mode, the OR[1:2] flag output is triple registerbuffered, and the IR[1:2] flag output is double register-buffered. Relevant timing diagrams for FWFT mode can be found in Figure 13, 14, 15 and 18.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PROGRAMMING FLAG OFFSETS Full and Empty Flag offset values are user programmable. The IDT72T36135M have internal registers for these offsets. There are eight default offset values selectable during Master Reset. These offset values are shown in Table 1. Offset values can also be programmed into the FIFO in one of two ways; serial or parallel loading method. The selection of the loading method is done using the LD (Load) pin. During Master Reset, the state of the LD input determines whether serial or parallel flag offset programming is enabled. A HIGH on LD during Master Reset selects serial loading of offset values. A LOW on LD during Master Reset selects parallel loading of offset values. In addition to loading offset values into the FIFO, it is also possible to read the current offset values. Offset values can be read via the parallel output port Q0-Qn, regardless of the programming mode selected (serial or parallel). It is not possible to read the offset values in serial fashion. Figure 3, Programmable Flag Offset Programming Sequence, summaries the control pins and sequence for both serial and parallel programming modes. For a more detailed description, see discussion that follows. The offset registers may be programmed (and reprogrammed) any time after Master Reset, regardless of whether serial or parallel programming has been selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIMING SELECTION The IDT72T36135M can be configured during the Master Reset cycle with either synchronous or asynchronous timing for PAF[1:2] and PAE[1:2] flags by use of the PFM pin. If synchronous PAF/PAE[1:2] configuration is selected (PFM, HIGH during MRS), the PAF is asserted and updated on the rising edge of WCLK only and not RCLK. Similarly, PAE[1:2] is asserted and updated on the rising edge of RCLK only and not WCLK. For detail timing diagrams, see Figure 22 for synchronous PAF[1:2] timing and Figure 23 for synchronous PAE[1:2] timing. If asynchronous PAF/PAE[1:2] configuration is selected (PFM, LOW during MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF[1:2] is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE[1:2] is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE[1:2] is reset to HIGH on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see Figure 24 for asynchronous PAF[1:2] timing and Figure 25 for asynchronous PAE[1:2] timing.
TABLE 1 -- DEFAULT PROGRAMMABLE TABLE 2 -- STATUS FLAGS FOR IDT FLAG OFFSETS STANDARD MODE
IDT72T36135M
*LD H L L L L H H H *LD H L FSEL1 L H L L H H L H FSEL1 X X FSEL0 L L H L H L H H FSEL0 X X Offsets n,m 1,023 511 255 127 63 31 15 7 Program Mode Serial(3) Parallel(4)
Number of Words in FIFO IDT72T36135M
0 1 to n (1) n + 1 to (524,288-(m+1)) (524,288-m) to 524,287 524,288
FF
H H H H L
PAF PAE
H H H L L L L H H H
EF
L H H H H
NOTE: 1. See Table 1 for values for n, m.
TABLE 3 -- STATUS FLAGS FOR FWFT MODE
IDT72T36135M Number of Words in FIFO
0 1 to n+1 n + 1 to (524,289-(m+1)) (524,289-m) to 524,288 524,289
IR
L L L L H
PAF PAE
H H H L L L L H H H
OR
H L L L L
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*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO MEMORY.
NOTES: 1. n = empty offset for PAE[1:2]. 2. m = full offset for PAF[1:2]. 3. As well as selecting serial programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1. 4. As well as selecting parallel programming mode, one of the default values will also be loaded depending on the state of FSEL0 & FSEL1.
NOTE: 1. See Table 1 for values for n, m.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
LD 0
WEN 0
REN 1
SEN 1
WCLK
RCLK X
SCLK X
IDT72T36135M Parallel write to registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) Parallel read from registers: Empty Offset (LSB) Empty Offset (MSB) Full Offset (LSB) Full Offset (MSB) Serial shift into registers:
0
1
0
1
X
X
0
1
1
0
X
X
38 bits for the IDT72T36135M 1 bit for each rising SCLK edge Starting with Empty Offset (LSB) Ending with Full Offset (MSB) X X X No Operation Write Memory Read Memory No Operation
6723 drw08
X 1 1 1
1 0 X 1
1 X 0 1
1 X X X
X
X X
X X X
X
NOTES: 1. The programming method can only be selected at Master Reset. 2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected. 3. The programming sequence applies to both IDT Standard and FWFT modes.
D/Q17 D/Q16
1st Parallel Offset Write/Read Cycle Data Inputs/Outputs D/Q0 EMPTY OFFSET (LSB) REGISTER 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
# of Bits Used
D/Q17 D/Q16
2nd Parallel Offset Write/Read Cycle Data Inputs/Outputs EMPTY OFFSET (MSB) REGISTER
4666 drw 06
D/Q0
19 18 17
D/Q17 D/Q16
3rd Parallel Offset Write/Read Cycle Data Inputs/Outputs FULL OFFSET (LSB) REGISTER 16 15 14 13 12 11 10 9 8 7 6 5 4 3
D/Q 0
21
4th Parallel Offset Write/Read Cycle
D/Q17 D/Q16
Data Inputs/Outputs FULL OFFSET (MSB) REGISTER
4666 drw 06
D/Q 0
19 18 17
6723 drw09
NOTE: 1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please refer to Figure 21, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
Figure 3. Programmable Flag Offset Programming Sequence 16
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SERIAL PROGRAMMING MODE If Serial Programming mode has been selected, as described above, then programming of PAE[1:2] and PAF[1:2] values can be achieved by using a combination of the LD, SEN, SCLK and SI input pins. Programming PAE[1:2] and PAF[1:2] proceeds as follows: when LD and SEN are set LOW, data on the SI input are written, one bit for each SCLK rising edge, starting with the Empty Offset LSB and ending with the Full Offset MSB. 38 bits total required. See Figure 19, Serial Loading of Programmable Flag Registers, for the timing diagram for this mode. Using the serial method, individual registers cannot be programmed selectively. PAE[1:2] and PAF[1:2] can show a valid status only after the complete set of bits (for all offset registers) has been entered. The registers can be reprogrammed as long as the complete set of new offset bits is entered. When LD is LOW and SEN is HIGH, no serial write to the registers can occur. Write operations to the FIFO are allowed before and during the serial programming sequence. In this case, the programming of all offset bits does not have to occur at once. A select number of bits can be written to the SI input and then, by bringing LD and SEN HIGH, data can be written to FIFO memory via Dn by toggling WEN. When WEN is brought HIGH with LD and SEN restored to a LOW, the next offset bit in sequence is written to the registers via SI. If an interruption of serial programming is desired, it is sufficient either to set LD LOW and deactivate SEN or to set SEN LOW and deactivate LD. Once LD and SEN are both restored to a LOW level, serial offset programming continues. From the time serial programming has begun, neither programmable flag will be valid until the full set of bits required to fill all the offset registers has been written. Measuring from the rising SCLK edge that achieves the above criteria; PAF[1:2] will be valid after three more rising WCLK edges plus tPAF, PAE[1:2] will be valid after the next three rising RCLK edges plus tPAE. It is only possible to read the flag offset values via the parallel output port Qn. PARALLEL MODE If Parallel Programming mode has been selected, as described above, then programming of PAE[1:2] and PAF[1:2] values can be achieved by using a combination of the LD, WCLK , WEN and Dn input pins. Programming PAE[1:2] and PAF[1:2] proceeds as follows: LD and WEN must be set LOW. When programming the Offset Registers of the TeraSync FIFO's the number of programming cycles will be based on the bus width, the following rules apply: 4 enabled write cycles are required to program the offset registers, (2 per offset). Data on the inputs Dn are written into the Empty Offset Register on the first two LOW-to-HIGH transition of WCLK. Upon the third and fourth LOW-toHIGH transition of WCLK, data are written into the Full Offset Register. See Figure 3, Programmable Flag Offset Programming Sequence for more details. RETRANSMIT FROM MARK OPERATION The Retransmit from Mark feature allows FIFO data to be read repeatedly starting at a user-selected position. The FIFO is first put into retransmit mode that will `mark' a beginning word and also set a pointer that will prevent ongoing FIFO write operations from over-writing retransmit data. The retransmit data can be read repeatedly any number of times from the `marked' position. The FIFO can be taken out of retransmit mode at any time to allow normal device operation. The `mark' position can be selected any number of times, each selection over-
writing the previous mark location. Retransmit operation is available in both IDT standard and FWFT modes. During IDT standard mode the FIFO is put into retransmit mode by a Lowto-High transition on RCLK when the `MARK' input is HIGH and EF[1:2] is HIGH. The rising RCLK edge `marks' the data present in the FIFO output register as the first retransmit data. The FIFO remains in retransmit mode until a rising edge on RCLK occurs while MARK is LOW. Once a `marked' location has been set (and the device is still in retransmit mode, MARK is HIGH), a retransmit can be initiated by a rising edge on RCLK while the retransmit input (RT) is LOW. REN must be HIGH (reads disabled) before bringing RT LOW. The device indicates the start of retransmit setup by setting EF[1:2] LOW, also preventing reads. When EF[1:2] goes HIGH, retransmit setup is complete and read operations may begin starting with the first data at the MARK location. Since IDT standard mode is selected, every word read including the first `marked' word following a retransmit setup requires a LOW on REN (read enabled). Note, write operations may continue as normal during all retransmit functions, however write operations to the `marked' location will be prevented. See Figure 17, Retransmit from Mark (IDT standard mode), for the relevant timing diagram. During FWFT mode the FIFO is put into retransmit mode by a rising RCLK edge when the `MARK' input is HIGH and OR[1:2] is LOW. The rising RCLK edge `marks' the data present in the FIFO output register as the first retransmit data. The FIFO remains in retransmit mode until a rising RCLK edge occurs while MARK is LOW. Once a marked location has been set (and the device is still in retransmit mode, MARK is HIGH), a retransmit can be initiated by a rising RCLK edge while the retransmit input (RT) is LOW. REN must be HIGH (reads disabled) before bringing RT LOW. The device indicates the start of retransmit setup by setting OR[1:2] HIGH. When OR[1:2] goes LOW, retransmit setup is complete and on the next rising RCLK edge after retransmit setup is complete, (RT goes HIGH), the contents of the first retransmit location are loaded onto the output register. Since FWFT mode is selected, the first word appears on the outputs regardless of REN, a LOW on REN is not required for the first word. Reading all subsequent words requires a LOW on REN to enable the rising RCLK edge. See Figure 18, Retransmit from Mark timing (FWFT mode), for the relevant timing diagram. Note, there must be a minimum of 128 words of data between the write pointer and read pointer when the MARK is asserted. Also, once the MARK is set, the write pointer will not increment past the "marked" location until the MARK is deasserted. This prevents "overwriting" of retransmit data. HSTL/LVTTL I/O Both the write port and read port are user selectable between HSTL or LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other control pins are selectable via SHSTL, see Table 4 for details of groupings. Note, that when the write port is selected for HSTL mode, the user can reduce the power consumption (in stand-by mode by utilizing the WCS input). All "Static Pins" must be tied to VCC or GND. These pins are LVTTL only, and are purely device configuration pins.
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TABLE 4 -- I/O CONFIGURATION
WHSTL SELECT WHSTL: HIGH = HSTL LOW = LVTTL Dn (I/P) WCLK/WR (I/P) WEN (I/P) WCS (I/P) RHSTL SELECT RHSTL: HIGH = HSTL LOW = LVTTL RCLK/RD (I/P) RCS (I/P) MARK (I/P) REN (I/P) OE (I/P) RT (I/P) Qn (O/P) EF/OR[1:2] (O/P) PAF[1:2] (O/P) PAE[1:2] (O/P) FF/IR[1:2] (O/P) TDO (O/P) SHSTL SELECT SHSTL: HIGH = HSTL LOW = LVTTL SCLK (I/P) LD (I/P) MRS (I/P) TCK (I/P) TMS (I/P) SEN (I/P) FWFT/SI (I/P) PRS (I/P) TRST (I/P) TDI (I/P) STATIC PINS LVTTL ONLY ASYR (I/P) FSEL1 (I/P) SHSTL (I/P) RHSTL (I/P) ASYW (I/P) FSEL0 (I/P) PFM (I/P) WHSTL (I/P)
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SIGNAL DESCRIPTION INPUTS:
DATA IN (D0 - Dn) Data inputs for 36-bit wide data (D0 - D35).
CONTROLS:
MASTER RESET ( MRS ) A Master Reset is accomplished whenever the MRS input is taken to a LOW state. This operation sets the internal read and write pointers to the first location of the RAM array. PAE[1:2] will go LOW, PAF[1:2] will go HIGH. If FWFT/SI is LOW during Master Reset then the IDT Standard mode, along with EF[1:2] and FF[1:2] are selected. EF[1:2] will go LOW and FF[1:2] will go HIGH. If FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with IR[1:2] and OR[1:2], are selected. OR[1:2] will go HIGH and IR[1:2] will go LOW. All control settings such as RM and PFM are defined during the Master Reset cycle. During a Master Reset, the output register is initialized to all zeroes. A Master Reset is required after power up, before a write operation can take place. MRS is asynchronous. See Figure 8, Master Reset Timing, for the relevant timing diagram. PARTIAL RESET (PRS) A Partial Reset is accomplished whenever the PRS input is taken to a LOW state. As in the case of the Master Reset, the internal read and write pointers are set to the first location of the RAM array, PAE[1:2] goes LOW, PAF[1:2] goes HIGH. Whichever mode is active at the time of Partial Reset, IDT Standard mode or First Word Fall Through, that mode will remain selected. If the IDT Standard mode is active, then FF[1:2] will go HIGH and EF[1:2] will go LOW. If the First Word Fall Through mode is active, then OR[1:2] will go HIGH, and IR[1:2] will go LOW. Following Partial Reset, all values held in the offset registers remain unchanged. The programming method (parallel or serial) currently active at the time of Partial Reset is also retained. The output register is initialized to all zeroes. PRS is asynchronous. A Partial Reset is useful for resetting the device during the course of operation, when reprogramming programmable flag offset settings may not be convenient. See Figure 9, Partial Reset Timing, for the relevant timing diagram. ASYNCHRONOUS WRITE (ASYW) The write port can be configured for either Synchronous or Asynchronous mode of operation. If during Master Reset the ASYW input is LOW, then Asynchronous operation of the write port will be selected. During Asynchronous operation of the write port the WCLK input becomes WR input, this is the Asynchronous write strobe input. A rising edge on WR will write data present on the Dn inputs into the FIFO. (WEN must be tied LOW when using the write port in Asynchronous mode). When the write port is configured for Asynchronous operation the full flag (FF[1:2]) operates in an asynchronous manner, that is, the full flag will be updated based in both a write operation and read operation. Note, if Asynchronous mode is selected, FWFT is not permissable. Refer to Figures 30, 31, 34 and 35 for relevant timing and operational waveforms.
ASYNCHRONOUS READ (ASYR) The read port can be configured for either Synchronous or Asynchronous mode of operation. If during a Master Reset the ASYR input is LOW, then Asynchronous operation of the read port will be selected. During Asynchronous operation of the read port the RCLK input becomes RD input, this is the Asynchronous read strobe input. A rising edge on RD will read data from the FIFO via the output register and Qn port. (REN must be tied LOW during Asynchronous operation of the read port). The OE input provides three-state control of the Qn output bus, in an asynchronous manner. (RCS, provides three-state control of the read port in Synchronous mode). When the read port is configured for Asynchronous operation the device must be operating on IDT standard mode, FWFT mode is not permissible if the read port is Asynchronous. The Empty Flag (EF[1:2]) operates in an Asynchronous manner, that is, the empty flag will be updated based on both a read operation and a write operation. Refer to figures 32, 33, 34 and 35 for relevant timing and operational waveforms. RETRANSMIT (RT) The Retransmit (RT) input is used in conjunction with the MARK input, together they provide a means by which data previously read out of the FIFO can be reread any number of times. If retransmit operation has been selected (i.e. the MARK input is HIGH), a rising edge on RCLK while RT is LOW will reset the read pointer back to the memory location set by the user via the MARK input. If IDT standard mode has been selected the EF[1:2] flag will go LOW and remain LOW for the time that RT is held LOW. RT can be held LOW for any number of RCLK cycles, the read pointer being reset to the marked location. The next rising edge of RCLK after RT has returned HIGH, will cause EF[1:2] to go HIGH, allowing read operations to be performed on the FIFO. The next read operation will access data from the `marked' memory location. Subsequent retransmit operations may be performed, each time the read pointer returning to the `marked' location. See Figure 17, Retransmit from Mark (IDT Standard mode) for the relevant timing diagram. If FWFT mode has been selected the OR[1:2] flag will go HIGH and remain HIGH for the time that RT is held LOW. RT can be held LOW for any number of RCLK cycles, the read pointer being reset to the `marked' location. The next RCLK rising edge after RT has returned HIGH, will cause OR[1:2] to go LOW and due to FWFT operation, the contents of the marked memory location will be loaded onto the output register, a read operation being required for all subsequent data reads. Subsequent retransmit operations may be performed each time the read pointer returning to the `marked' location. See Figure 18, Retransmit from Mark (FWFT mode) for the relevant timing diagram. MARK The MARK input is used to select Retransmit mode of operation. An RCLK rising edge while MARK is HIGH will mark the memory location of the data currently present on the output register, the device will also be placed into retransmit mode. For the IDT72T36135M a minimum of 128 words (x36). Also, once the MARK is set, the write pointer will not increment past the "marked" location until the MARK is deasserted. This prevents "overwriting" of retransmit data. The MARK input must remain HIGH during the whole period of retransmit mode, a falling edge of RCLK while MARK is LOW will take the device out of retransmit mode and into normal mode. Any number of MARK locations can be set during FIFO operation, only the last marked location taking effect. Once a
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mark location has been set the write pointer cannot be incremented past this marked location. During retransmit mode write operations to the device may continue without hindrance. FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI) This is a dual purpose pin. During Master Reset, the state of the FWFT/ SI input determines whether the device will operate in IDT Standard mode or First Word Fall Through (FWFT) mode. If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode will be selected. This mode uses the Empty Flag (EF[1:2]) to indicate whether or not there are any words present in the FIFO memory. It also uses the Full Flag function (FF[1:2]) to indicate whether or not the FIFO memory has any free space for writing. In IDT Standard mode, every word read from the FIFO, including the first, must be requested using the Read Enable (REN) and RCLK. If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be selected. This mode uses Output Ready (OR[1:2]) to indicate whether or not there is valid data at the data outputs (Qn). It also uses Input Ready (IR[1:2]) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to Qn after three RCLK rising edges, REN = LOW is not necessary. Subsequent words must be accessed using the Read Enable (REN) and RCLK. After Master Reset, FWFT/SI acts as a serial input for loading PAE[1:2] and PAF[1:2] offsets into the programmable registers. The serial input function can only be used when the serial loading method has been selected during Master Reset. Serial programming using the FWFT/SI pin functions the same way in both IDT Standard and FWFT modes. WRITE STROBE & WRITE CLOCK (WR/WCLK) If Synchronous operation of the write port has been selected via ASYW, this input behaves as WCLK. A write cycle is initiated on the rising edge of the WCLK input. Data setup and hold times must be met with respect to the LOW-to-HIGH transition of the WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the FF/ IR[1:2], and PAF[1:2] flags will not be updated. The Write and Read Clocks can either be independent or coincident. If Asynchronous operation has been selected this input is WR (write strobe). Data is Asynchronously written into the FIFO via the Dn inputs whenever there is a rising edge on WR. In this mode the WEN input must be tied LOW. WRITE ENABLE (WEN) When the WEN input is LOW, data may be loaded into the FIFO RAM array on the rising edge of every WCLK cycle if the device is not full. Data is stored in the RAM array sequentially and independently of any ongoing read operation. When WEN is HIGH, no new data is written in the RAM array on each WCLK cycle. To prevent data overflow in the IDT Standard mode, FF[1:2] will go LOW, inhibiting further write operations. Upon the completion of a valid read cycle, FF[1:2] will go HIGH allowing a write to occur. The FF[1:2] is updated by two WCLK cycles + tSKEW after the RCLK cycle. To prevent data overflow in the FWFT mode, IR[1:2] will go HIGH, inhibiting further write operations. Upon the completion of a valid read cycle, IR[1:2] will go LOW allowing a write to occur. The IR[1:2] flag is updated by two WCLK cycles + tSKEW after the valid RCLK cycle. WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode. If Asynchronous operation of the write port has been selected, then WEN must be held active, (tied LOW). 20
READ STROBE & READ CLOCK (RD/RCLK) If Synchronous operation of the read port has been selected via ASYR, this input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK input. Data can be read on the outputs, on the rising edge of the RCLK input. It is permissible to stop the RCLK. Note that while RCLK is idle, the EF/OR[1:2], and PAE[1:2] flags will not be updated. The Write and Read Clocks can be independent or coincident. If Asynchronous operation has been selected this input is RD (Read Strobe) . Data is Asynchronously read from the FIFO via the output register whenever there is a rising edge on RD. In this mode the REN and RCS inputs must be tied LOW. The OE input is used to provide Asynchronous control of the threestate Qn outputs. WRITE CHIP SELECT (WCS) The WCS disables all Write Port inputs (data only) if it is held HIGH. To perform normal operations on the write port, the WCS must be enabled, held LOW. READ ENABLE (REN) When Read Enable is LOW, data is loaded from the RAM array into the output register on the rising edge of every RCLK cycle if the device is not empty. When the REN input is HIGH, the output register holds the previous data and no new data is loaded into the output register. The data outputs Q0-Qn maintain the previous data value. In the IDT Standard mode, every word accessed at Qn, including the first word written to an empty FIFO, must be requested using REN provided that RCS is LOW. When the last word has been read from the FIFO, the Empty Flag (EF[1:2]) will go LOW, inhibiting further read operations. REN is ignored when the FIFO is empty. Once a write is performed, EF[1:2] will go HIGH allowing a read to occur. The EF[1:2] flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle. Both RCS and REN must be active, LOW for data to be read out on the rising edge of RCLK. In the FWFT mode, the first word written to an empty FIFO automatically goes to the outputs Qn, on the third valid LOW-to-HIGH transition of RCLK + tSKEW after the first write. REN and RCS do not need to be asserted LOW for the First Word to fall through to the output register. In order to access all other words, a read must be executed using REN and RCS. The RCLK LOW-to-HIGH transition after the last word has been read from the FIFO, Output Ready (OR[1:2]) will go HIGH with a true read (RCLK with REN = LOW;RCS = LOW), inhibiting further read operations. REN is ignored when the FIFO is empty. If Asynchronous operation of the Read port has been selected, then REN must be held active, (tied LOW). SERIAL ENABLE ( SEN ) The SEN input is an enable used only for serial programming of the offset registers. The serial programming method must be selected during Master Reset. SEN is always used in conjunction with LD. When these lines are both LOW, data at the SI input can be loaded into the program register one bit for each LOW-to-HIGH transition of SCLK. When SEN is HIGH, the programmable registers retains the previous settings and no offsets are loaded. SEN functions the same way in both IDT Standard and FWFT modes. OUTPUT ENABLE ( OE ) When Output Enable is enabled (LOW), the parallel output buffers receive data from the output register. When OE is HIGH, the output data bus (Qn) goes into a high impedance state. During Master or a Partial Reset the OE is the only input that can place the output bus Qn, into High-Impedance. During Reset the RCS input can be HIGH or LOW, it has no effect on the Qn outputs.
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READ CHIP SELECT ( RCS ) The Read Chip Select input provides synchronous control of the Read output port. When RCS goes LOW, the next rising edge of RCLK causes the Qn outputs to go to the Low-Impedance state. When RCS goes HIGH, the next RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master or Partial Reset the RCS input has no effect on the Qn output bus, OE is the only input that provides High-Impedance control of the Qn outputs. If OE is LOW the Qn data outputs will be Low-Impedance regardless of RCS until the first rising edge of RCLK after a Reset is complete. Then if RCS is HIGH the data outputs will go to High-Impedance. The RCS input does not effect the operation of the flags. For example, when the first word is written to an empty FIFO, the EF[1:2] will still go from LOW to HIGH based on a rising edge of RCLK, regardless of the state of the RCS input. Also, when operating the FIFO in FWFT mode the first word written to an empty FIFO will still be clocked through to the output register based on RCLK, regardless of the state of RCS. For this reason the user must take care when a data word is written to an empty FIFO in FWFT mode. If RCS is disabled when an empty FIFO is written into, the first word will fall through to the output register, but will not be available on the Qn outputs which are in HIGH-Z. The user must take RCS active LOW to access this first word, place the output bus in LOW-Z. REN must remain disabled HIGH for at least one cycle after RCS has gone LOW. A rising edge of RCLK with RCS and REN active LOW, will read out the next word. Care must be taken so as not to lose the first word written to an empty FIFO when RCS is HIGH. Refer to Figure 16, RCS and REN Read Operation (FWFT Mode). The RCS pin must also be active (LOW) in order to perform a Retransmit. See Figure 12 for Read Cycle and Read Chip Select Timing (IDT Standard Mode). See Figure 15 for Read Cycle and Read Chip Select Timing (First Word Fall Through Mode). If Asynchronous operation of the Read port has been selected, then RCS must be held active, (tied LOW). OE provides three-state control of Qn. WRITE PORT HSTL SELECT (WHSTL) The control inputs, data inputs and flag outputs associated with the write port can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master Reset, then HSTL operation of the write port will be selected. If WHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs and outputs associated with the write port are listed in Table 4, I/O Configuration. READ PORT HSTL SELECT (RHSTL) The control inputs, data inputs and flag outputs associated with the read port can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW at Master Reset, then LVTTL will be selected for the read port. The inputs and outputs associated with the read port are listed in Table 4, I/O Configuration. SYSTEM HSTL SELECT (SHSTL) All inputs not associated with the write and read port can be setup to be either HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation of all the inputs not associated with the write and read port will be selected. If SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs associated with SHSTL are listed in Table 4, I/O Configuration. LOAD (LD) This is a dual purpose pin. During Master Reset, the state of the LD input, along with FSEL0 and FSEL1, determines one of eight default offset values for the PAE[1:2] and PAF[1:2] flags, along with the method by which these offset 21
registers can be programmed, parallel or serial (see Table 1). After Master Reset, LD enables write operations to and read operations from the offset registers. Only the offset loading method currently selected can be used to write to the registers. Offset registers can be read only in parallel. After Master Reset, the LD pin is used to activate the programming process of the flag offset values PAE[1:2] and PAF[1:2]. Pulling LD LOW will begin a serial loading or parallel load or read of these offset values. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE OR READ DATA TO/FROM THE FIFO MEMORY. PROGRAMMABLE FLAG MODE (PFM) During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on PFM will select Synchronous Programmable flag timing mode. If asynchronous PAF/PAE[1:2] configuration is selected (PFM, LOW during MRS), the PAE[1:2] is asserted LOW on the LOW-to-HIGH transition of RCLK. PAE[1:2] is reset to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF[1:2] is asserted LOW on the LOW-to-HIGH transition of WCLK and PAF[1:2] is reset to HIGH on the LOW-to-HIGH transition of RCLK. If synchronous PAE/PAF[1:2] configuration is selected (PFM, HIGH during MRS) , the PAE[1:2] is asserted and updated on the rising edge of RCLK only and not WCLK. Similarly, PAF[1:2] is asserted and updated on the rising edge of WCLK only and not RCLK. The mode desired is configured during master reset by the state of the Programmable Flag Mode (PFM) pin.
OUTPUTS:
FULL FLAG ( FF/IR[1:2] ) This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF[1:2]) function is selected. When the FIFO is full, FF[1:2] will go LOW, inhibiting further write operations. When FF[1:2] is HIGH, the FIFO is not full. If no reads are performed after a reset (either MRS or PRS), FF[1:2] will go LOW after D writes to the FIFO (D = 524,288 for the IDT72T36135M). See Figure 10, Write Cycle and Full Flag Timing (IDT Standard Mode), for the relevant timing information. Please see Flagging section for external gating instructions of these flags. In FWFT mode, the Input Ready (IR[1:2]) function is selected. IR[1:2] goes LOW when memory space is available for writing in data. When there is no longer any free space left, IR[1:2] goes HIGH, inhibiting further write operations. If no reads are performed after a reset (either MRS or PRS), IR[1:2] will go HIGH after D writes to the FIFO (D = 524,288 for the IDT72T36135M). See Figure 13, Write Timing (FWFT Mode), for the relevant timing information. The IR[1:2] status not only measures the contents of the FIFO memory, but also counts the presence of a word in the output register. Thus, in FWFT mode, the total number of writes necessary to deassert IR[1:2] is one greater than needed to assert FF[1:2] in IDT Standard mode. FF/IR[1:2] is synchronous and updated on the rising edge of WCLK. FF/ IR[1:2] are double register-buffered outputs. Note, when the device is in Retransmit mode, this flag is a comparison of the write pointer to the `marked' location. This differs from normal mode where this flag is a comparison of the write pointer to the read pointer. EMPTY FLAG ( EF/OR[1:2] ) This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (EF[1:2]) function is selected. When the FIFO is empty, EF[1:2] will go LOW, inhibiting further read operations. When EF[1:2] is HIGH, the FIFO is not empty. See Figure 11, Read Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for the relevant timing information. Please see Flagging section for external gating instructions of these flags.
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In FWFT mode, the Output Ready (OR[1:2]) function is selected. OR[1:2] goes LOW at the same time that the first word written to an empty FIFO appears valid on the outputs. OR[1:2] stays LOW after the RCLK LOW to HIGH transition that shifts the last word from the FIFO memory to the outputs. OR[1:2] goes HIGH only with a true read (RCLK with REN = LOW). The previous data stays at the outputs, indicating the last word was read. Further data reads are inhibited until OR[1:2] goes LOW again. See Figure 14, Read Timing (FWFT Mode), for the relevant timing information. EF/OR[1:2] is synchronous and updated on the rising edge of RCLK. In IDT Standard mode, EF[1:2] is a double register-buffered output. In FWFT mode, OR[1:2] is a triple register-buffered output. PROGRAMMABLE ALMOST-FULL FLAG ( PAF[1:2] ) The Programmable Almost-Full flag (PAF[1:2]) will go LOW when the FIFO reaches the almost-full condition. In IDT Standard mode, if no reads are performed after reset (MRS), PAF[1:2] will go LOW after (D - m) words are written to the FIFO. The PAF[1:2] will go LOW after (524,288-m) writes for the IDT72T36135M. The offset "m" is the full offset value. The default setting for this value is stated in the footnote of Table 2, Status Flags for IDT Standard Mode. Please see Flagging section for external gating instructions of these flags. In FWFT mode, the PAF[1:2] will go LOW after (524,289-m) writes for the IDT72T36135M, where m is the full offset value. The default setting for this value is stated in Table 3, Status Flags for FWFT Mode. See Figure 22, Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information.
If asynchronous PAF[1:2] configuration is selected, the PAF[1:2] is asserted LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF[1:2] is reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous PAF[1:2] configuration is selected, the PAF[1:2] is updated on the rising edge of WCLK. See Figure 24, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT Mode). Note, when the device is in Retransmit mode, this flag is a comparison of the write pointer to the `marked' location. This differs from normal mode where this flag is a comparison of the write pointer to the read pointer. PROGRAMMABLE ALMOST-EMPTY FLAG ( PAE[1:2] ) The Programmable Almost-Empty flag (PAE[1:2]) will go LOW when the FIFO reaches the almost-empty condition. In IDT Standard mode, PAE[1:2] will go LOW when there are n words or less in the FIFO. The offset "n" is the empty offset value. The default setting for this value is stated in the footnote of Table 1. Please see Flagging section for external gating instructions of these flags. In FWFT mode, the PAE[1:2] will go LOW when there are n+1 words or less in the FIFO. The default setting for this value is stated in Table 1. See Figure 23, Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Mode), for the relevant timing information. If asynchronous PAE[1:2] configuration is selected, the PAE[1:2] is asserted LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE[1:2] is reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous PAE[1:2] configuration is selected, the PAE[1:2] is updated on the rising edge of RCLK. See Figure 25, Asynchronous Programmable AlmostEmpty Flag Timing (IDT Standard and FWFT Mode).
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CONSIDERATIONS FOR READING FLAG OUTPUTS On this device, there are two sets of flagging outputs for the empty flag (EF1 & EF2), full flag (FF1 & FF2), Programmable Almost Empty Flag (PAE1 & PAE2), and Programmable Almost Full Flag (PAF1 & PAF2) the user must work with in order to be able to correctly read the status of each flag. Since this device is a multi-chip module (MCM), both die's flags must be read accordingly to avoid skewing problems between the two internal die. To remedy this function, the user must tie together FF1 & FF2, and EF1 & EF2 flag outputs to an external gate from a neighboring programmable device such as an FPGA or PLD and read from the output of the logical gate. An OR
IDT72T36135M
gate is used for FWFT mode and an AND gate is used for IDT mode. This must be done to avoid timing skew problems between the two sets of flags. For the PAE[1:2] and PAF[1:2] active low output flags, the user has the option to leave the PAE[1:2] and PAF[1:2] as is and use both pins at different programmable water marks for measuring buffer status. Please see the section on Parallel Programming Mode to understand how to program these two sets of flags as different water marks in Functional Description section of the datasheet. This gives added flexibility for queue management. Below is an example diagram for how this is accomplished.
EF1
EF2
FF1
FF2
PAE1
PAE2
PAF1
PAF2
OPTIONAL GATE (1) GATE (1) AND GATE AND GATE
EF
FF
PAE
PAF
6723 drw10
NOTE: 1. An "OR" Gate is used for FWFT mode, and an "AND" Gate is used for IDT Standard mode.
Figure 4. Output Flag Gating Considerations
PIN COMPATIBILITY WITH 9M TERASYNC (IDT72T36125) CONSIDERATIONS The IDT72T36135M can be a drop and replacement for the 9M TeraSync (IDT72T36125) if specific pin changes are made to the 18M FIFO. Since the 18M TeraSync is a Multi-Chip Module (MCM), containing two 9M TeraSyncs (IDT72T18125) in width expansion mode, certain functionality can not be offered in the 18M TeraSync such as bus matching, single flag outputs and
interspersed parity. From these changes, the 18M FIFO has removed specific inputs such as IW, OW, BM, BE, IP, while also gaining another set of output flags as specified in Considerations for Reading Flag Outputs which are EF2, FF2, PAE2, and PAF2. To maintain drop-in replacement compatibility for the 18M TeraSync, the pin changes on the pin diagram for the 18M TeraSync FIFO from the 9M TeraSync FIFO have been identified, and listed in the table below.
TABLE 5 -- PIN CHANGES BETWEEN 9M TERASYNC AND 18M TERASYNC
9M TeraSync FIFO (IDT72T36125) pins changed BM IP IW OW HF EREN ERCLK BE 18M TeraSync FIFO (IDT72T36135M) new pins EF2 PAE2 NC (No Connect) NC (No Connect) PAF2 FF2 NC (No Connect) GND
NOTES: 1. Internally, the 9M pins on the left side of the table will be tied to the GND or VDD plane, respectively in the 18M device. 2. Please see IDT72T36125 TeraSync FIFO datasheet for additional features listed.
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JTAG FUNCTIONALITY AND CONFIGURATION
The IDT72T36135M is composed of two independent memory arrays, and thus cannot be treated as a single JTAG device in the scan chain. The two arrays (A and B) each have identical characteristics and commands but must be treated as separate entities in JTAG operations. Please refer to Figure 5, JTAG Configuration for IDT72T36135M.
JTAG signaling must be provided serially to each array and utilize the information provided in the Scan Register Descriptions, JTATG Instruction Description. Specifically, commands for Array B must precede those Array A in any JTAG operations sent to the IDT72T36135M. Please reference Application Note AN-411, "JTAG Testing of Multichip Modules" for specific instructions on performing JTAG testing on the IDT72T36135M. AN-411 is available at www.idt.com.
TDI
Array A
TDOA
TDIB
Array B
TDO
TCK TMS TRST
6723 drw11
Figure 5. JTAG Configuration for IDT72T36135M
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JTAG TIMING SPECIFICATION
tTCK t4 t1
TCK
t2
t3
TDI/ TMS
tDS
TDO
tDH
TDO
t6
TRST
Notes to diagram: t1 = tTCKLOW t2 = tTCKHIGH t3 = tTCKFALL t4 = tTCKRISE t5 = tRST (reset pulse width) t6 = tRSR (reset recovery)
tDO
6723 drw12
t5
(vcc = 2.5V 5%; Tcase = 0C to +85C)
Parameter Symbol
JTAG AC ELECTRICAL CHARACTERISTICS
Test Conditions IDT72T36135M Min. JTAG Clock Input Period tTCK JTAG Clock HIGH JTAG Clock Low JTAG Clock Rise Time JTAG Clock Fall Time JTAG Reset JTAG Reset Recovery tTCKHIGH tTCKLOW tTCKRISE tTCKFALL tRST tRSR 100 40 40 50 50 Max. Units 5(1) 5(1) ns ns ns ns ns ns ns
SYSTEM INTERFACE PARAMETERS
IDT72T36135M Parameter Data Output Data Output Hold Data Input Symbol tDO(1) tDOH(1) tDS tDH trise=3ns tfall=3ns Test Conditions Min. 0 10 10 Max. Units 20 -
ns ns ns
NOTE: 1. 50pf loading on external output signals.
NOTE: 1. Guaranteed by design.
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* * *
JTAG INTERFACE
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to support the JTAG boundary scan interface. The IDT72T36135M incorporates the necessary tap controller and modified pad cells to implement the JTAG facility. Note that IDT provides appropriate Boundary Scan Description Language program files for these devices. The Standard JTAG interface consists of four basic elements: * Test Access Port (TAP)
TAP controller Instruction Register (IR) Data Register Port (DR)
The following sections provide a brief description of each element. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). The Figure below shows the standard Boundary-Scan Architecture
DeviceID Reg. Boundary Scan Reg. Bypass Reg.
Mux
TDO TDI
T A
TMS TCLK TRST
P TAP Controller
clkDR, ShiftDR UpdateDR
Instruction Decode clklR, ShiftlR UpdatelR Instruction Register
Control Signals
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Figure 6. Boundary Scan Architecture
TEST ACCESS PORT (TAP) The Tap interface is a general-purpose port that provides access to the internal of the processor. It consists of four input ports (TCLK, TMS, TDI, TRST) and one output port (TDO). 26
THE TAP CONTROLLER The Tap controller is a synchronous finite state machine that responds to TMS and TCLK signals to generate clock and control signals to the Instruction and Data Registers for capture and update of data.
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
Test-Logic Reset 0 1 1 1 SelectIR-Scan 1 0 Capture-IR 0 Shift-IR 1 1 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0
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0
Run-Test/ Idle
SelectDR-Scan 0 1 Capture-DR 00 Shift-DR 1
0
Input = TMS
Exit1-DR 00 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0
1
0
NOTES: 1. Five consecutive TCK cycles with TMS = 1 will reset the TAP. 2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS). 3. TAP controller must be reset before normal FIFO operations can begin.
Figure 7. TAP Controller State Diagram
Refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1) for the full state diagram All state transitions within the TAP controller occur at the rising edge of the TCLK pulse. The TMS signal level (0 or 1) determines the state progression that occurs on each TCLK rising edge. The TAP controller takes precedence over the FIFO memory and must be reset after power up of the device. See TRST description for more details on TAP controller reset. Test-Logic-Reset All test logic is disabled in this controller state enabling the normal operation of the IC. The TAP controller state machine is designed in such a way that, no matter what the initial state of the controller is, the Test-Logic-Reset state can be entered by holding TMS at high and pulsing TCK five times. This is the reason why the Test Reset (TRST) pin is optional. Run-Test-Idle In this controller state, the test logic in the IC is active only if certain instructions are present. For example, if an instruction activates the self test, then it will be executed when the controller enters this state. The test logic in the IC is idles otherwise. Select-DR-Scan This is a controller state where the decision to enter the Data Path or the Select-IR-Scan state is made. Select-IR-Scan This is a controller state where the decision to enter the Instruction Path is made. The Controller can return to the Test-Logic-Reset state other wise. 27
Capture-IR In this controller state, the shift register bank in the Instruction Register parallel loads a pattern of fixed values on the rising edge of TCK. The last two significant bits are always required to be "01". Shift-IR In this controller state, the instruction register gets connected between TDI and TDO, and the captured pattern gets shifted on each rising edge of TCK. The instruction available on the TDI pin is also shifted in to the instruction register. Exit1-IR This is a controller state where a decision to enter either the PauseIR state or Update-IR state is made. Pause-IR This state is provided in order to allow the shifting of instruction register to be temporarily halted. Exit2-DR This is a controller state where a decision to enter either the ShiftIR state or Update-IR state is made. Update-IR In this controller state, the instruction in the instruction register is latched in to the latch bank of the Instruction Register on every falling edge of TCK. This instruction also becomes the current instruction once it is latched. Capture-DR In this controller state, the data is parallel loaded in to the data registers selected by the current instruction on the rising edge of TCK. Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and Update-IR states in the Instruction path.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SCAN REGISTER DESCRIPTIONS
THE INSTRUCTION REGISTER The Instruction register allows an instruction to be shifted in serially into the processor at the rising edge of TCLK. The Instruction is used to select the test to be performed, or the test data register to be accessed, or both. The instruction shifted into the register is latched at the completion of the shifting process when the TAP controller is at UpdateIR state. The instruction register must contain 8 bit instruction register-based cells which can hold instruction data. These mandatory cells are located nearest the serial outputs they are the least significant bits. TEST DATA REGISTER The Test Data register contains three test data registers: the Bypass, the Boundary Scan register and Device ID register. These registers are connected in parallel between a common serial input and a common serial data output. The following sections provide a brief description of each element. For a complete description, refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). TEST BYPASS REGISTER The register is used to allow test data to flow through the device from TDI to TDO. It contains a single stage shift register for a minimum length in serial path. When the bypass register is selected by an instruction, the shift register stage is set to a logic zero on the rising edge of TCLK when the TAP controller is in the Capture-DR state. The operation of the bypass register should not have any effect on the operation of the device in response to the BYPASS instruction. THE BOUNDARY-SCAN REGISTER The Boundary Scan Register allows serial data TDI be loaded in to or read out of the processor input/output ports. The Boundary Scan Register is a part of the IEEE 1149.1-1990 Standard JTAG Implementation. THE DEVICE IDENTIFICATION REGISTER The Device Identification Register is a Read Only 64-bit register used to specify the manufacturer, part number and version of the processor to be determined through the TAP in response to the IDCODE instruction. IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity is dropped in the 11-bit Manufacturer ID field. For the IDT72T36135M, the Part Number field contains the following values: Device Part# Field IDT72T36135M 0417 31(MSB) 28 27 12 11 1 0(LSB) Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit) 0X0 0X33 1
IDT72T36135M JTAG Device Identification Register
JTAG INSTRUCTION REGISTER The Instruction register allows instruction to be serially input into the device when the TAP controller is in the Shift-IR state. The instruction is decoded to perform the following: * Select test data registers that may operate while the instruction is current. The other test data registers should not interfere with chip operation and the selected data register. * Define the serial test data register path that is used to shift data between TDI and TDO during data register scanning. The Instruction Register is a 8 bit field (i.e.IR3, IR2, IR1, IR0 per die) to decode 32 different possible instructions. Instructions are decoded as follows. Please note: Again, since this device is a two die MCM, the JTAG instructions must be shifted in twice during JTAG testing. To account for each dies 4bit instruction registers for a total of 8 bits altogether.
JTAG INSTRUCTION DESCRIPTION
Hex Value 0x00 0x22 0x11 0x33 0xFF Instruction EXTEST IDCODE SAMPLE/PRELOAD HIGH-IMPEDANCE BYPASS Function Select Boundary Scan Register Select Chip Identification data register Select Boundary Scan Register JTAG Select Bypass Register
JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For a complete description refer to the IEEE Standard Test Access Port Specification (IEEE Std. 1149.1-1990). EXTEST The required EXTEST instruction places the IC into an external boundarytest mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register is accessed to drive test data off-chip via the boundary outputs and receive test data off-chip via the boundary inputs. As such, the EXTEST instruction is the workhorse of IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts and of logic cluster function. IDCODE The optional IDCODE instruction allows the IC to remain in its functional mode and selects the optional device identification register to be connected between TDI and TDO. The device identification register is a 64-bit shift register containing information regarding the IC manufacturer, device type, and version code. Accessing the device identification register does not interfere with the operation of the IC. Also, access to the device identification register should be immediately available, via a TAP data-scan operation, after power-up of the IC or after the TAP has been reset using the optional TRST pin or by otherwise moving to the Test-Logic-Reset state. SAMPLE/PRELOAD The required SAMPLE/PRELOAD instruction allows the IC to remain in a normal functional mode and selects the boundary-scan register to be connected between TDI and TDO. During this instruction, the boundary-scan register can be accessed via a date scan operation, to take a sample of the functional data entering and leaving the IC. This instruction is also used to preload test data into the boundary-scan register before loading an EXTEST instruction.
Please note: The IDT72T36135M device is a two die MCM which means 64 bits will be shifted out of the device when the user is in IDCODE. Since the JTAG device identification register is 32 bits per die.
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
HIGH-IMPEDANCE The optional High-Impedance instruction sets all outputs (including two-state as well as three-state types) of an IC to a disabled (high-impedance) state and selects the one-bit bypass register to be connected between TDI and TDO. During this instruction, data can be shifted through the bypass register from TDI to TDO without affecting the condition of the IC outputs.
BYPASS The required BYPASS instruction allows the IC to remain in a normal functional mode and selects the one-bit bypass register to be connected between TDI and TDO. The BYPASS instruction allows serial data to be transferred through the IC from TDI to TDO without affecting the operation of the IC.
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
tRS MRS tRSS REN tRSS WEN tRSS FWFT/SI tRSS LD tRSS FSEL0, FSEL1 tHRSS WHSTL tHRSS RHSTL tHRSS SHSTL tRSS PFM tRSS RT tRSS SEN tRSF EF/OR[1:2] tRSF FF/IR[1:2] tRSF PAE[1:2] tRSF PAF[1:2] tRSF Q0 - Qn tRSR tRSR tRSR tRSR
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
If FWFT = HIGH, OR = HIGH If FWFT = LOW, EF = LOW If FWFT = LOW, FF = HIGH If FWFT = HIGH, IR = LOW
OE = HIGH
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OE = LOW NOTE: 1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset is complete.
Figure 8. Master Reset Timing
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COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PRS tRSS REN tRSS WEN tRSS RT tRSS SEN
tRS tRSR
tRSR
tRSF EF/OR [1:2] tRSF FF/IR [1:2] PAE [1:2] PAF [1:2] tRSF Q0 - Qn tRSF
If FWFT = HIGH, OR = HIGH If FWFT = LOW, EF = LOW If FWFT = LOW, FF = HIGH If FWFT = HIGH, IR = LOW
tRSF
OE = HIGH OE = LOW
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NOTE: 1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset is complete.
Figure 9. Partial Reset Timing
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
tCLKH 2 tDS DX tWFF FF[1:2] tWFF tDH tCLK tCLK
L
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
NO WRITE
NO WRITE
WCLK D0 - Dn
tSKEW1
(1)
1
tSKEW1
(1)
1
2
tDS DX+1 tWFF
tDH
tWFF
WEN RCLK tENS REN tENS RCS tA Q0 - Qn tRCSLZ
DATA READ
tENH
tENS
tENH
tA
NEXT DATA READ
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NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF[1:2] will go HIGH (after one WCLK cycle pus tWFF). If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF[1:2] deassertion may be delayed one extra WCLK cycle. 2. LD = HIGH, OE = LOW, EF[1:2] = HIGH. 3. WCS = LOW.
Figure 10. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLKH
tCLK
tCLKL tENS tENH tENS tENH
RCLK
tENS tENH
1
2
REN
tREF
NO OPERATION
NO OPERATION
tREF tA LAST WORD LAST WORD tOHZ
(1)
tREF
EF[1:2]
tA tA D0 D1
Q0 - Qn
tOLZ tOE
tOLZ
OE
tSKEW1
WCLK
tENS tENH tENS tENH
WEN
tWCSS tWCSH tDH tDS D1
6723 drw18
WCS
tDS tDH
D0 - Dn
D0
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF[1:2] will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF[1:2] deassertion may be delayed one extra RCLK cycle. 2. LD = HIGH. 3. First data word latency = tSKEW1 + 1*TRCLK + tREF. 4. RCS is LOW.
Figure 11. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode) 32
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2
RCLK
tENS
REN
tENS tENH tENS tENS tREF
RCS
tREF tRCSH
Z
EF[1:2]
tRCSLZ tA LAST DATA-1
tRCSHZ tRCSLZ
tA LAST DATA tSKEW1(1)
Q0 - Qn WCLK
tENS
tENH
WEN
tDS tDH Dx
6723 drw19
Dn
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF[1:2] will go HIGH (after one RCLK cycle plus tREF). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF[1:2] deassertion may be delayed one extra RCLK cycle. 2. LD = HIGH. 3. First data word latency = tSKEW1 + 1*TRCLK + tREF. 4. OE is LOW.
Figure 12. Read Cycle and Read Chip Select (IDT Standard Mode)
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WCLK
1
WEN tDS W3 W4 tSKEW2(2)
2 3 1 2
tENS tDS W[n +2] W[n+3] W[n+4] W[D-m-2] W[D-m-1] W[D-m] W[D-m+1] W[D-m+2] W[D-1] W[
D- +1 2 1
tDS
tDH
tDS W[
D- +2 2 1
tENH WD
D0 - Dn
W1
W2
]
]
W[
D- +3 2 1
]
tSKEW1(1)
RCLK
1
RCS
tENS
REN tRCSLZ tA W1 tREF
Q0 - Qn
PREVIOUS DATA IN OUTPUT REGISTER
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
OR[1:2]
PAE[1:2]
tPAES
tPAFS
PAF[1:2] tWFF
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34
Figure 13. Write Timing (First Word Fall Through Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IR[1:2]
NOTES: 1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that OR[1:2] will go LOW after two RCLK cycles plus tREF. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then OR[1:2] assertion may be delayed one extra RCLK cycle. 2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE[1:2] will go HIGH after one RCLK cycle plus tPAES. If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE[1:2] deassertion may be delayed one extra RCLK cycle. 3. LD = HIGH, OE = LOW 4. n = PAE[1:2] offset, m = PAF[1:2] offset and D = maximum FIFO depth. 5. D = 524,289 for the IDT72T36135M. 6. First data word latency = tSKEW1 + 2*TRCLK + tREF.
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WCLK 2 tSKEW2
(2)
tENS
tENH
1 (1) tSKEW1
WEN
tDS
tDH
D0 - Dn
WD
RCLK
1
tENS
tENS
REN
OE tA tA tA W3 Wm+2 W[m+3] W[m+4]
2 W[ D-1 + 1 ] 2 W[ D-1 + 2 ]
tOHZ tA W[D-n-1] W[D-n] W[D-n+1] W[D-n+2] W[D-1] tA tA W2
tOE
Q0 - Qn
W1
W1
WD tREF
OR[1:2] tPAES
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
PAE[1:2] tPAFS
PAF[1:2] tWFF
tWFF
IR[1:2]
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35
NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR[1:2] will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the IR[1:2] assertion may be delayed one extra WCLK cycle. 2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF[1:2] will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF[1:2] deassertion may be delayed one extra WCLK cycle. 3. LD = HIGH. 4. n = PAE[1:2] Offset, m = PAF[1:2] offset and D = maximum FIFO depth. 5. D = 524,289 for the IDT72T36135M. 6. RCS = LOW.
Figure 14. Read Timing (First Word Fall Through Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAY 29, 2006
WCLK
2 tSKEW2
(2)
tENS
tENH
1 (1) tSKEW1
WEN
tDS
tDH
D0 - Dn
WD
RCLK
1
tENS
tENS
REN
tENS
tENH
RCS
tRCSLZ tA tA W3 Wm+2 W[m+3] W[m+4]
2 W[ D-1 + 1 ] 2 W[ D-1 + 2 ]
tRCSHZ tA W[D-n-1] W[D-n] W[D-n+1] W[D-n+2] W[D-1] tA tA W2
Q0 - Qn
W1
WD tREF
OR[1:2]
tPAES
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
PAE[1:2]
tPAFS
PAF[1:2]
tWFF
tWFF
IR[1:2]
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36
NOTES: 1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that IR[1:2] will go LOW after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the IR[1:2] assertion may be delayed one extra WCLK cycle. 2. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF[1:2] will go HIGH after one WCLK cycle plus tPAFS. If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF[1:2] deassertion may be delayed one extra WCLK cycle. 3. LD = HIGH. 4. n = PAE[1:2] Offset, m = PAF[1:2] offset and D = maximum FIFO depth. 5. D = 524,289 for the IDT72T36135M. 6. OE = LOW.
Figure 15. Read Cycle and Read Chip Select Timing (First Word Fall Through Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAY 29, 2006
RCLK
1 2 3
tENS
tENH
tENS
REN tENS tENS tENH tENS
RCS tREF tREF
OR [1:2] tRCSLZ tA
W1 W2
tRCSHZ
tRCSLZ
W2
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HIGH-Z
Qn
1st Word falls through to O/P register on this cycle
tSKEW
WCLK tENH
tENS
WEN tDS
W2
tDS
tDH
tDH
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
Dn
W1
37
NOTES: 1. It is very important that the REN be held HIGH for at least one cycle after RCS has gone LOW. If REN goes LOW on the same cycle as RCS or earlier, then Word, W1 will be lost, Word, W2 will be read on the output when the bus goes to LOW-Z. 2. The 1st Word will fall through to the output register regardless of REN and RCS. However, subsequent reads require that both REN and RCS be active, LOW.
Figure 16 . RCS and REN Read Operation (FWFT Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MAY 29, 2006
RCLK
1 2 3
tENS tENS
tENS
REN tA tA tA WMK+n WMK WMK+1 tENH tENS tENH tA WMK tENS tA WMK+1
tA
Qn
WMK-
1
MARK
RT tREF tREF
EF [1:2] tPAES(6)
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
PAE [1:2] tSKEW2
1 2
WCLK tENS
38
WEN tPAFS
PAF [1:2]
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NOTES: 1. Retransmit setup is complete when EF[1:2] returns HIGH. 2. OE = LOW;RCS = LOW. 3. RT must be HIGH when reading from FIFO. 4. Once MARK is set, the write pointer will not increment past the `marked' location, preventing overwrites of Retransmit data. 5. Before a "MARK" can be set there must be at least 64 number of words of data between the Write Pointer and Read Pointer locations. 6. A transition in the PAE[1:2] flag may occur one RCLK cycle earlier than shown, (on cycle 2).
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
Figure 17. Retransmit from Mark (IDT Standard Mode)
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RCLK
1 2 3
tENS tENS
tENS
REN tA tA tA WMK WMK+1 WMK+1 WMK+n tENH tENS tENH tA tA WMK tENS tA WMK+2
tA
Qn
WMK-1
MARK
RT tREF tREF
OR [1:2] tPAES(6)
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
PAE [1:2] tSKEW2
1 2
WCLK tENS
39
tPAFS
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WEN
PAF [1:2]
NOTES: 1. Retransmit setup is complete when OR[1:2] returns LOW. 2. OE = LOW;RCS = LOW. 3. RT must be HIGH when reading from FIFO. 4. Once MARK is set, the write pointer will not increment past the `marked' location, preventing overwrites of Retransmit data. 5. Before a "MARK" can be set there must be at least 64 number of words of data between the Write Pointer and Read Pointer locations. 6. A transition in the PAE[1:2] flag may occur one RCLK cycle earlier than shown, (on cycle 2).
Figure 18. Retransmit from Mark (First Word Fall Through Mode)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
tSCLK tSCKL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tSCKH
SCLK
tSENS tSENH tENH
SEN
tLDS tLDS tLDH
LD
tSDS tSDH
BIT 19 EMPTY OFFSET BIT 1
FULL OFFSET
SI
BIT 1
BIT 19
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Figure 19. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK tCLKH tCLKL
WCLK
tLDS tLDH tLDH
LD
tENS tENH tENH
WEN
tDS tDH
PAE OFFSET PAF OFFSET
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tDH
D0 - Dn
Figure 20. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK tCLKH tCLKL
RCLK
tLDS tLDH tLDS tLDH tLDS tLDH
LD
tENH tENS tENS tENH tENS tENH
REN
tA tA PAE OFFSET VALUE PAF OFFSET VALUE tA PAE OFFSET
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Q0 - Qn
DATA IN OUTPUT REGISTER
NOTES: 1. OE = LOW. 2. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
Figure 21. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) 40
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tCLKL
tCLKL 1 tENS tENH 2 1 2
WCLK WEN
tPAFS
tPAFS
D - m words in FIFO
(2)
PAF [1:2] RCLK
D - (m +1) words in FIFO
(2)
D-(m+1) words (2) in FIFO
tSKEW2
(3)
tENS
tENH
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REN
NOTES: 1. m = PAF[1:2] offset. 2. D = maximum FIFO depth. In IDT Standard mode: D = 524,288 for the IDT72T36135M. In FWFT mode: D = 524,289 for the IDT72T36135M. 3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF[1:2] will go HIGH (after one WCLK cycle plus tPAFS). If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF[1:2] deassertion time may be delayed one extra WCLK cycle. 4. PAF[1:2] is asserted and updated on the rising edge of WCLK only. 5. Select this mode by setting PFM HIGH during Master Reset.
Figure 22. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS tENH
WEN PAE [1:2] RCLK REN
n words in FIFO , (3) n + 1 words in FIFO
(2)
tSKEW2 1
(4)
tPAES 2 tENS
n + 1 words in FIFO , (3) n + 2 words in FIFO
(2)
n words in FIFO , (3) n + 1 words in FIFO
(2)
tPAES 1 2
tENH
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NOTES: 1. n = PAE[1:2] offset. 2. For IDT Standard mode 3. For FWFT mode. 4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE[1:2] will go HIGH (after one RCLK cycle plus tPAES). If the time between the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE[1:2] deassertion may be delayed one extra RCLK cycle. 5. PAE[1:2] is asserted and updated on the rising edge of WCLK only. 6. Select this mode by setting PFM HIGH during Master Reset. 7. RCS = LOW.
Figure 23. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes) 41
MAY 29, 2006
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
tCLKH WCLK tENS WEN tPAFA PAF[1:2] D - (m + 1) words in FIFO D - m words in FIFO tPAFA RCLK tENS REN tENH tCLKL
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
D - (m + 1) words in FIFO
6723 drw31
NOTES: 1. m = PAF[1:2] offset. 2. D = maximum FIFO Depth. In IDT Standard Mode: D = 524,288 for the IDT72T36135M. In FWFT Mode: D = 524,289 for the IDT72T36135M. 3. PAF[1:2] is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition. 4. Select this mode by setting PFM LOW during Master Reset. 5. RCS = LOW.
Figure 24. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH WCLK
tCLKL
tENS WEN
tENH
PAE[1:2]
n words in FIFO(2), n + 1 words in FIFO(3)
tPAEA
n + 1 words in FIFO(2), n + 2 words in FIFO(3)
n words in FIFO(2), n + 1 words in FIFO(3)
tPAE
A
RCLK tENS REN
6723 drw22
NOTES: 1. n = PAE[1:2] offset. 2. For IDT Standard Mode. 3. For FWFT Mode. 4. PAE[1:2] is asserted LOW on RCLK transition and reset to HIGH on WCLK transition. 5. Select this mode by setting PFM LOW during Master Reset. 6. RCS = LOW.
Figure 25. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes) 42
MAY 29, 2006
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RCLK REN tENS tENH tA Qn FF[1:2] tFFA WR tDS Dn tDH WD WD+1
6723 drw23
W0 tFFA tCYC tFFA tCYH
W1
NOTE: 1. OE = LOW, WEN = LOW and RCS = LOW.
Figure 26. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
RCLK REN Qn EF[1:2]
tSKEW
1
2
tENS tA Last Word tREF tCYL W0
tEN
H
tA W1 tREF
WR
tDS
tCYH tCYC tDH W0 tDS W1
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tDH
Dn
NOTE: 1. OE = LOW, WEN = LOW and RCS = LOW.
Figure 27. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
43
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
No Write
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
WCLK WEN Dn
1
2
DF tWFF
DF+1 tWFF
FF[1:2] tSKEW RD tAA Qn Last Word WX tAA WX+1
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tCYC tCYL tCYH
NOTE: 1. OE = LOW, RCS = LOW and REN = LOW. 2. Asynchronous Read is available in IDT Standard Mode only.
Figure 28. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
WCLK tENS WEN tDS Dn W0 tEFA tRPE RD tEFA tCYH tAA Qn Last Word in Output Register W0
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tENH
tDH
EF[1:2]
NOTE: 1. OE = LOW, REN = LOW and RCS = LOW. 2. Asynchronous Read is available in IDT Standard Mode only.
Figure 29. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
44
MAY 29, 2006
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
tCYH
WR
tCYC
tCY
L
tDH
Dn W0
tDS
W1
tDH
RD
tAA
Qn Last Word in O/P Register W0
tAA
W1
tEFA
EF[1:2]
tRPE
tEFA
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NOTES: 1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW 2. Asynchronous Read is available in IDT Standard Mode only.
Figure 30. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
tCYC tCYH WR tDS Dn tCYC tCYH RD tAA Qn Wx tFFA FF[1:2]
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tCYL
tDH Wy
tDS
tDH
Wy+1
tCYL tAA Wx+1 Wx+2 tFFA
NOTES: 1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW. 2. Asynchronous Read is available in IDT Standard Mode only.
Figure 31. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
45
MAY 29, 2006
IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION Word width may be increased by connecting together the control signals of multiple devices plus using external gating logic. Status flags can be gated and detected from the gate output. The EF[1:2], FF[1:2], PAE[1:2], and PAF[1:2]
flags should be gated using logical gates to remove the possibility of clock skew between the two device(s) outputs. Figure 32 demonstrates a width expansion using two IDT72T36135M devices. D0 - D35 from each device form a 72-bit wide input bus and Q0-Q35 from each device form a 72-bit wide output bus. Any word width can be attained by adding additional IDT72T36135M devices.
PROGRAMMABLE ALMOST FULL SERIAL CLOCK (SCLK) PARTIAL RESET (PRS) MASTER RESET (MRS) FIRST WORD FALL THROUGH/ SERIAL INPUT (FWFT/SI) RETRANSMIT (RT) Dm+1 - Dn m+n DATA IN D0 - Dm
FIFO#1 AND GATE AND GATE AND GATE FIFO#1 GATE (1) FIFO#2 GATE (1)
FULL FLAG/INPUT READY
FIFO#1
(PAF)
FIFO#2
GATE (1) GATE (1) FIFO#1
GATE (1)
(FF/IR)
FIFO#2
GATE (1)
(EF/OR)
FIFO#2
AND GATE
AND GATE
(PAE)
AND GATE
m
n
EMPTY FLAG/OUTPUT READY READ CLOCK (RCLK) READ CHIP SELECT (RCS) READ ENABLE (REN)
PROGRAMMABLE ALMOST EMPTY
WRITE CLOCK (WCLK) WRITE ENABLE (WEN)
OUTPUT ENABLE (OE) LOAD (LD) FULL FLAG/INPUT READY (FF/IR) #1 FULL FLAG/INPUT READY (FF/IR) #1
GATE (1)
FULL FLAG/INPUT READY (FF/IR)) #2 IDT 72T36135M FIFO #1 IDT 72T36135M PROGRAMMABLE ALMOST FULL (PAF) #1 FIFO #2 PROGRAMMABLE ALMOST FULL (PAF) #2 EMPTY FLAG/OUTPUT READY (EF/OR) #1
GATE (1)
FULL FLAG/INPUT READY (FF/IR) #2 PROGRAMMABLE ALMOST FULL (PAF) #1 PROGRAMMABLE ALMOST FULL (PAF) #2
AND GATE
AND GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #1
GATE (1)
EMPTY FLAG/OUTPUT READY (EF/OR) #2 PROGRAMMABLE ALMOST EMPTY (PAE) #1 PROGRAMMABLE ALMOST EMPTY (PAE) #2
GATE (1)
EMPTY FLAG/OUTPUT READY (EF/OR) #2 PROGRAMMABLE ALMOST EMPTY (PAE) #1 PROGRAMMABLE ALMOST EMPTY (PAE) #2
(4)
AND GATE
(4)
AND GATE
m Q0 - Qm
n
Qm+1 - Qn
m+n DATA OUT
6723 drw39
NOTES: 1. An OR gate is used for FWFT mode, AND gate for IDT mode. 2. Do not connect any output control signals directly together. 3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths. 4. PAE/PAF[1:2] optional, see section of external gating of output flags. 5. Recommend IDT74LVC32A 2-Input Positive OR Gate. Recommend IDT74LVC08A 2-Input AND Gate.
Figure 32. Block Diagram of 524,288 x 72 Width Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY) The IDT72T36135M can easily be adapted to applications requiring depths greater than and 524,288 with an 36-bit bus width. In FWFT mode, the FIFOs can be connected in series (the data outputs of one FIFO connected to the data inputs of the next) with no external logic necessary. The resulting configuration provides a total depth equivalent to the sum of the depths associated with each single FIFO. Figure 33 shows a depth expansion using two IDT72T36135M devices. For depth expansion mode option #1, "logical OR gates" need to be used to drive the active low input WEN and REN pins respectively from the active low 46
output OR[1:2] and IR[1:2] pins. Two sets of OR gates are used in this mode to derive a feedback loop to the REN and WEN pins to avoid writing or reading to/from a device when the device is not ready to accept data. The 2nd row of OR gates take in the IR or OR pin's status and allow for data to be written/read to the next FIFO in the chain. If the IR or OR pins are low, this will enable the device to accept writes or reads from the next device in line. To use this mode, the FIFO device's clock speed depends on the added prop delay of the "OR" gates and setup time between the two FIFO devices. Example, if the "OR" gates being used have a combined 10ns propagation delay, a 1ns jitter budget, and 1ns clock skew margin, 12ns must be taken into account during each clock cycle.
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IDT72T36135M 2.5V 18M-BIT TeraSync 36-BIT FIFO 524,288 x 36
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
For instance, a 25MHz clock has around a 40ns clock cycle. For a 45% - 55% clock duty cycle, 18ns account for 45% of the duty cycle when the clock is high. This means, 18ns - 12ns = 6ns of setup time for data to be available at the 2nd IDT FIFO which is fine considering the setup time for this FIFO is around 1.5ns. Designers must leave an adequate timing window to allow data to be captured by the 2nd IDT FIFO. Please take this into consideration when using this depth expansion mode to avoid data meta-stability issues. For buffering greater than 18Mbits at higher frequencies, IDT recommends using the IDT Sequential Flow Controller (SFC). Please see IDT Flow-Control Management (FCM) product web site for more information on the SFC. Care should be taken to select FWFT mode during Master Reset for all FIFOs in the depth expansion configuration. The first word written to an empty configuration will pass from one FIFO to the next ("ripple down") until it finally appears at the outputs of the last FIFO in the chain - no read operation is necessary but the RCLK of each FIFO must be free-running. Each time the data word appears at the outputs of one FIFO, that device's OR[1:2] line goes LOW, enabling a write to the next FIFO in line. OR gates are used to take in the considerations of the next FIFO in the chains IR pin status. If the IR pins are Low, this will enable the device to accept writes from upstream devices. For an empty expansion configuration, the amount of time it takes for OR[1:2] of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's outputs) after a word has been written to the first FIFO is the sum of the delays for each individual FIFO and the sum of the OR gate prop delays: (N - 1)*(4*transfer clock) + 3*TRCLK + 2 *OR prop delay where N is the number of FIFOs in the expansion and TRCLK is the RCLK period. Note that extra cycles should be added for the possibility that the tSKEW1 specification is not met between WCLK and transfer clock, or RCLK and transfer clock, for the OR[1:2] flag.
FWFT/SI TRANSFER CLOCK WRITE CLOCK WRITE ENABLE INPUT READY FWFT/SI WCLK WEN IR RCLK OR1 OR2
OR GATE
The "ripple down" delay is only noticeable for the first word written to an empty depth expansion configuration. There will be no delay evident for subsequent words written to the configuration. The first free location created by reading from a full depth expansion configuration will "bubble up" from the last FIFO to the previous one until it finally moves into the first FIFO of the chain. Each time a free location is created in one FIFO of the chain, that FIFO's IR[1:2] line goes LOW, enabling the preceding FIFO to write a word to fill it. For a full expansion configuration, the amount of time it takes for IR[1:2] of the first FIFO in the chain to go LOW after a word has been read from the last FIFO is the sum of the delays for each individual FIFO and the sum of the OR gate prop delays: (N - 1)*(3*transfer clock) + 2 TWCLK + 2 *OR prop delay where N is the number of FIFOs in the expansion and TWCLK is the WCLK period. Note that extra cycles should be added for the possibility that the tSKEW1 specification is not met between RCLK and transfer clock, or WCLK and transfer clock, for the IR[1:2] flag. The Transfer Clock line should be tied to either WCLK or RCLK, whichever is faster. Both these actions result in data moving, as quickly as possible, to the end of the chain and free locations to the beginning of the chain. Depth Expansion Option #2 is depicted in Figure 34, Depth Expansion Option#2. One device will be active at a time by toggling the WCS pins. Data will be written into FIFO in Ping Pong fashion. First data is written into FIFO#1, second data is written into FIFO#2, third data is written into FIFO#1, fourth data is written into FIFO#2, and so on. Data can then be read out in the same manner on the read side by toggling the RCS1 and RCS2.
WCLK
OR GATE
FWFT/SI
RCLK RCS
READ CLOCK READ CHIP SELECT READ ENABLE OUTPUT READY OUTPUT ENABLE n DATA OUT
6723 drw40
WEN
OR GATE
IDT 72T36135M
REN RCS OE
OR GATE
IR1 IR2
IDT 72T36135M
REN OR OE
DATA IN
n Dn
Qn
GND n Dn
Qn
Figure 33. Depth Expansion Option #1
FF1 WCS1 IDT 72T36135M #1 EF1 RCS1
36
36
REN RCS2
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WEN WCS2 FF2
IDT 72T36135M #2 EF2
Figure 34. Depth Expansion Option #2 47
MAY 29, 2006
ORDERING INFORMATION
IDT XXXXX X XX X Package X Device Type Power Speed X Process / Temperature Range BLANK I(1) G BB 5 6 Commercial (0 C to +70 C) Industrial (-40 C to +85 C) Green Plastic Ball Grid Array (PBGA, BB240-1) Commercial Only Commercial and Industrial Clock Cycle Time (tCLK) Speed in Nanoseconds
L
Low Power
72T36135M 524,288 x 36 2.5V 18M-Bit High-Speed TeraSync FIFO
6723 drw42
NOTE: 1. Industrial temperature range product for 6ns speed grade is available as a standard device. All other speed grades are available by special order. 2. Green parts are available. For specific speeds and packages please contact your sales office.
DATASHEET DOCUMENT HISTORY
09/01/2005 02/28/2006 05/29/2006 pg. 1. pg. 10. pgs. 10, 21, and 23. CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 for SALES: 800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com
48
for Tech Support: 408-360-1753 email: FIFOhelp@idt.com

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